As the semiconductor devices have been recently miniaturized, wirings configuring a circuit have been also miniaturized. In order to avoid delay of a circuit operation, which is caused due to the increase of a wiring resistance resulting from the miniaturization, JP-A Nos. 2004-193431 and 2006-165129 disclose methods of reducing parasitic capacitance of the wirings. In JP-A Nos. 2004-193431 and 2006-165129, a method is used which deposits an insulation film under condition that a step coverage is worsened, by using a narrow interval between the neighboring wirings. Since the step coverage is poor in case of using the method, the insulation film is connected at upper parts of the respective neighboring wirings, resulting in forming a void at a central part between the wirings. The void can be used as an air gap part between the wirings. Since the air gap part has a dielectric constant lower than that of the insulation film, it is possible to reduce the parasitic capacitance of the wirings.